Metal interconnect structures are an important part of VLSI integrated circuits. The metal interconnect structures typically include metal lines and vias. The vias are used to interconnect the metal lines with conductive structures above and below the metal interconnect layer. The metal lines are also referred to as conductive lines. Sophisticated ICs may include several layers of metal interconnect structutes. The metal lines are commonly used on VLSI integrated circuits for carrying digital signals, analog signals, or bias power to and from the imbedded semiconductor devices.
The process of forming a metal interconnect structure begins with forming conductive plugs in an underlying dielectric layer. Next, a blanket deposition of a conductive material, such as aluminum, copper, or polysilicon is deposited over the conductive plugs and dielectric layer. Then, a photoresist layer is deposited over the metal layer. The photoresist layer is patterned and developed in accordance with the predetermined metal interconnect pattern. The developed photoresist layer is used as a mask for etching of the underlying metal layer.
This prior art method of patterning and etching a conductive metal layer is satisfactory where the underlying dielectric layer is relatively planar. However, as integrated circuits become more sophisticated and larger numbers of layers are stacked atop each other, the planarity of the underlying dielectric layer becomes unsatisfactory. Indeed, the difference between the top of the dielectric layer and a valley of the dielectric layer may be as much as 4,000-8,000 angstroms especially in the case of DRAM manufacture. The variance in topography presents significant etching difficulties where a photoresist layer is placed directly onto a metal layer. Specifically, when a metal layer is deposited onto the high topography dielectric layer, the metal layer tends to conform to the shape of the underlying dielectric layer. This causes the conductive metal layer to also have high topography variance and requires higher over etching. The high topography height dramatically increases difficulty in the photolithography process due to poor depth of focus.
As devices are shrinking down, deep ultraviolet (DUV) lithography is employed and the thickness of the DUV photoresist layer that is used to pattern the conducting layer is also reduced in order to improve photolithography resolution. However, this approach is also problematical because the etching selectivity of metal to photoresist is generally less than 2:1.
Therefore, what is needed is a method of etching conductive lines that lie atop a highly non-planar dielectric layer.